发明名称 |
Dynamic decoder input for semiconductor memory |
摘要 |
A decoder for address inputs to a semiconductor memory or the like comprises a NOR gate having a number of parallel input transistors corresponding to the number of address bits to be decoded. The address bits and their complements are selectively connected to the gates of the input transistors and the sources of these transistors, rather than only to the gates as in prior decoders. The layout of this decoder more nearly matches the pitch of rows in a high density dynamic RAM.
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申请公布号 |
US4330851(A) |
申请公布日期 |
1982.05.18 |
申请号 |
US19800133377 |
申请日期 |
1980.03.21 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
WHITE, JR., LIONEL S. |
分类号 |
G11C11/408;G11C11/418;H03K19/096;(IPC1-7):G11C11/40 |
主分类号 |
G11C11/408 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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