| 摘要 |
In order to provide fast data transfers and to ensure that the capacitive loading remains fixed, a data communication bus structure for interconnecting a desired number of subsystems of a data processing system comprises an integrated circuit (1) having bus conductors (50, 60, 70) of fixed length and a fixed number of ports (10, 20, 30) for connecting the subsystems. Each port comprises the control and data terminals for a group of driver/receiver circuits (11-13, 21-23, 31-33), each driver/receiver circuit of a group being connected to a respective bus conductor. Each driver/receiver circuit comprises a driver circuit having address and data output latches and driver gates, and a receiver circuit having address and data input latches. |
