发明名称 ANALOG ARITHMETIC CIRCUIT
摘要 PURPOSE:To realize an on-line checking of an analog circuit, by checking whether the monitor signal is equal to a prescribed value or not with no special operation nor any limit of instrumentation and under the using state. CONSTITUTION:A resistance R101 is put between the input terminal of an operational amplifier OP3 and a Zener diode ZD3, and the produced signal v5 for a checking is supplied to a resistance R104. At the same time, signals v1 and v2 are applied to resistances R102 and R103 respectively. As a result, a monitor signal VM equal to the sum of signals v1, and v2 and v5 is produced from an adder comprising resistances R102, R103, R104 and R105, a capacitor 101 and an operational amplifier OP4. When the sum of the signal v5 and the Zener voltage of a Zener diode ZD3 is less than the saturated voltage of the OP3, the signal v5 is equal to a signal obtained by inverting the polarity of the sum of signals v1 and v2 plus bias viltages vB and VS. As a result, the signal VM is equal to the sum VB and VS which are set at the constant value, and accordingly the signal VM also becomes constant. The constant value of the signal VM indicates that an analog arithmetic circuit is working in the normal way.
申请公布号 JPS5775376(A) 申请公布日期 1982.05.11
申请号 JP19800150174 申请日期 1980.10.28
申请人 TOKYO SHIBAURA DENKI KK 发明人 YANAGISAWA TADAHIRO
分类号 G06G7/12;G05B23/02;G06G7/02 主分类号 G06G7/12
代理机构 代理人
主权项
地址