Simultaneously forming fully implanted DMOS together with enhancement and depletion mode MOSFET devices

摘要

A semiconductor fabrication process and the resulting structure is disclosed for an FET device with a precisely defined channel length. Two process embodiments are described to make a diffused MOS device which does not require the use of p-type diffusions to obtain 1 micron channel length. Instead, to accurately define such micron-range channel lengths, a lateral etching technique is employed. To obtain well controlled threshold voltages, the channels are ion implanted. Thus the enhancement portion of the diffused MOS device channel is defined by an etching step instead of a diffusion step, thereby producing a channel having a length which is shorter and a threshold voltage which is better controlled than those which have been available in the prior art.