发明名称 INFORMATION PROCESSING DEVICE
摘要 PURPOSE:To read out a data of a buffer memory at a high speed, by indexing a part of an address converting buffer, concurrently with a logical address generating operation. CONSTITUTION:A logical address operated by a logical address operating circuit 106 is stored in a logical address register 107. Concurrently with generation of this logical address, auxiliary address converting buffers 408-410 are indexed by use of an unfinished logical address. Subsequently, indexing by directories 109', 109'' and read-out of a buffer memory body 110 are executed, concurrently with the fact that the address in the register 107 is converted to a real address by an address converting buffer 108. In this way, even if the capacity of the buffer memory becomes large, a data is read out at a high speed without increasing the number of lines of the buffer memory.
申请公布号 JPS5774876(A) 申请公布日期 1982.05.11
申请号 JP19800149773 申请日期 1980.10.24
申请人 NIPPON DENKI KK 发明人 OOMORI YUUZOU
分类号 G06F12/08;G06F12/10 主分类号 G06F12/08
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