发明名称 SAMPLE CLOCK GENERATOR
摘要 PURPOSE:To enable correspondence to television signals automatically different from synchronizing signal forms, by adopting a PLL with broad dynamic range and stopping the comparison of phase if no hrizontal synchronizing signal is present in the vertical synchronizing period. CONSTITUTION:When a synchronizing signal where no horizotal synchronizing signal exists at vertical synchronizing period is applied to a composite synchronizing signal input terminal 4, the output of an AND circuit 8 is absent, the output of a triggrable multivibrator 11 is inverted to be binary ''1'', and a vertical gate signal 13 of negative polarity is obtained at the output of a vertical synchronizing gate circuit 12. A reference gate circuit 14 blocks horizontal synchronizing signals, and a reproduction synchronzing gate circuit 15 blocks a reproduction synchronizing signal 16 and they are applied to a phase comparator 17. The output of the phase comparator 17 is applied to a voltage controlled oscillator 19 via a low pass filter 18. When a composite synchronizing signal is applied to an input terminal 4, the horizontal synchronizing signal 10 and the reproducing synchronizing signal 16 are applied to the phase comparator 17.
申请公布号 JPS5773574(A) 申请公布日期 1982.05.08
申请号 JP19800148299 申请日期 1980.10.24
申请人 HITACHI DENSHI KK 发明人 MORITA KENJI
分类号 H04N5/04;H04N5/06;H04N7/12 主分类号 H04N5/04
代理机构 代理人
主权项
地址