| 摘要 |
PURPOSE:To form a retriggarable characteristic with low power consumption and simple circuit constitution, by forming an I2L logical circuit with 4 inverters and a capacitor, and absorbing an intermittent trigger pulse. CONSTITUTION:When an H or L level signal inputted to an input terminal 1, an L or H level signal is obtained at an output terminal 2 via inverters 3, 4. Through the operation of an inverter 6 and a capacitor C1, if an input level is at L, the C1 starts charging with a time constant by the capacitance of the C1. An inverter 5 is connected in antiparallel with the inverter 4 and self-holds the output level of the inverter 4. When a grigger pulse A is inputted to the input terminal 1, the output terminal 2 is at H level, and when an intermittent state is finished at (b), a voltage increases as a curve (a) of Fig. B at the capacitor C1, and when this voltage reaches a prescribed voltage, the output terminal 2 is inverted into L level via the inverters 6, 5, 4 as shown in Fig. C. Thus, the intermittent pulse can be absorbed. |
