| 摘要 |
PURPOSE:To make a logical amplitude uniform even if an NAND gate is included in a logical operation circuit, by interposing a clamping diode between the gate of an FET and a reference potential. CONSTITUTION:In a time T2, through an FET Q4 is cut off, a current is flowed through a diode D0, and therefore, the voltage of -A becomes VST. In a time T4, the voltage of -A becomes VST also because a current is flowed through the diode D0, and thus, the ununiformity of the logical amplitude is eliminated. In a time T1, A and B are 1 and 0 respectively, and the voltage of -A becomes VSAT, and therefore, a current is not flowed to the diode D0 as usual. In a time T3, the operation is as usual also. Thus, waveforms -A and -B have only two states of the voltage VSAT and the voltage VST, and the ununiformity of the logical amplitude is improved. |
