| 摘要 |
The data processing system comprises a first central processing unit CPU, an interrupt controlling unit INT, a direct-memory access unit DMA, and a memory unit MEM connected together by a data bus B1. The circuit arrangement comprises first, second, third, and fourth means PM, SM, TM, QM which provide alarm signals upon detecting malfunctions in the central processing unit, the interrupt controller, the direct memory access unit, and the memory, respectively. A diagnosis unit UDG resets and disconnects the central processing unit from the data bus and is connected to the bus when an alarm signal is generated so as to carry out diagnosis programmes for detecting the faulty member. When correct functioning has been restored, the diagnosis unit reconnects the central processing unit to the data bus. <IMAGE> |
