| 摘要 |
An error detection circuit detects prolonged sequences of unchanged logic state in a data busing structure. The circuit generates a complementary two rail logic output from a pair of flip-flops. The circuit includes a comparator which compares the logic state of the data input from the bus with the output of one of the flip-flops, and which inputs alternate opposite logic states to that flip-flop as long as the data input exists for a time in the same logic state as the output of the one flip-flop during a cycle. The complementary two rail output changes every cycle to actively exercise the error detection circuit and prevent silent failures therein. The circuit is self-checking because internal failures yield non-complementary outputs.
|
