| 摘要 |
A digital data communication system typically includes arrangements for achieving synchronization of the digital data processed by the system. However, known synchronizing arrangements are usually inefficient with respect to the time required to achieve bit synchronization. To shorten the time required for synchronization of two bit streams, an improved synchronizer including a sequential store, a plurality of comparators, a circulating memory having a plurality of memory registers, and a control circuit is disclosed. A first bit stream is extended through the sequential store into respective first inputs of the plurality of comparators. Each bit of a second bit stream jointly feeds all respective second inputs of the comparators. Using negative logic, each comparator output is NANDed with a first memory register output and fed into a second register input. When all but one of the memory register outputs are set, synchronization is achieved. |
