| 摘要 |
PURPOSE:To reduce arithmetic errors greatly while simplifying circuit constitution, by correcting the high-order prescribed-bit data according to the contents of data one bit lower than the high-order prescribed-bit data of multiplicand data. CONSTITUTION:The contents of data one bit lower than the high-order prescribed- bit data of multiplicand data A are detected, and according to the detection result, the high-order prescribed bit of the multiplicand data A is corrected. On the basis of the corrected prescribed bit data, a full-adder circuit 4 adds the multiplicand data A and multiplier data B toghether and the addition output is latched by a latch circuit 18 to be sent out as arithmetic result data O7-O0 showing the high-order prescribed eight bits of the arithmetic result data A.B. |
