| 摘要 |
PURPOSE:To transmit and receive accurate series data by providing a buffer register BR between a shift register SR and a bus and controlling the transmission and reception of the SR according to the presence of data in the BR. CONSTITUTION:A series data input and output equipment S-I/O consists of an SR11 transmitting and receiving input and output data to and from an external equipment, a BR12 wherein those data are held temporarily, and a bus 13 connecting the input and output data to a CPU. Then, shift pulses phis to the SR11 are controlled by a reception mode FF21 inindicating the transmission and reception modes of the S-I/O and an FF22 controlling the transfer of data on the basis of the presence of data in the BR12, thereby preventing necessary data from being erased. When the final data is transferred to the BR12 of SR11, an enable series data input and output FF14 operating the S-I/O is reset through the operation of an auxiliary FF15 to prevent the transmission and reception of unnecessary data, performing the transmission and reception of accurate series data. |
