PROCESS FOR FORMING A POLYSILICON GATE INTEGRATED CIRCUIT DEVICE

摘要

In a process for forming a CMOS integrated circuit structure hav ing polysilicon gates (18, 24) and interconnections (19) which are all of the same conductivity type, preferably n+-type, polys ilicon is formed into the gate (18) for the n-FET, a barrier layer (20) for the p-FET region (15) and the interconnection pattern (19). Then a layer of arsenosilicate glass (ASG) (23) is formed over the n-FET active region (14), the interconnections (19) and in an area to define the p-FET gate (24) which is etched using the ASG layer (23) as a mask. The device is heated to drive in impurities from the ASG layer (23) to n+ dope the polysilicon and f orm the n-FET source and drain (27, 28). Boron is then implanted into the p-FET source and drain (25, 26), the ASG layer serving to mask the polysilicon from p-type doping. Since the polysilicon which is etched is undoped, highly accurate self alignment is ob tained.