Multiplexer for plesiochronous digital signal transmission - has high bit rate using data provided through low bit rate sub-system

摘要

The system for forming plesiochronous transmissions requires no greatly complex circuitry. The digital signals from each subsystem are stored in blocks in a shift register. Here the synchronising and pulse matching signals are added before transfer in blocks into the high speed transmission link. The signal block assembly is monitored by a phase comparator which sets a pulse deviation of plus or minus one bit in a counter. The multiplex frame is thus used to build a pseudo-frame. The synchronisation is fixed at one bit in each information block in the subsystem. Decoding at the receiving end can follow a similar process. The subsystem bit rate is typically about 8M bits per second. The application is to high speed multiplexed digital transmissions, for e.g at about 34M bits per second. At such speeds accurate synchronising at all times is problematic.