| 摘要 |
<p>A data processing system (10, 11, 12, 13) in which a unit (20, 22, 26, 28) needing to be serviced by a processor (10) first requests an interrupt and, after the interrupt is granted by the processor (10), requests access to a system bus (14) to transfer interrupt information as it normally would transfer other information. The interrupting unit (20, 22, 26, 28) must wait for other units having higher priority to transfer information, usually memory information over the bus (14), before it can access the bus (14) to transfer its interrupting information. This permits transfers of information having higher priority to occur before the interrupt information is transferred.</p> |
