| 摘要 |
PURPOSE:To reduce the number of parity generation circuits to a half and to simplify the circuit constitution in keeping the high-speed property during the partial writing action, by using the parity generating circuit in common to both an error correction code generation circuit and a syndrome generation circuit. CONSTITUTION:The information bit (f) is accepted from a memory array 1 during the reading action; the externally written data (d) is accepted in the first half of the writing axtion; and the bit (f) given from the array 1 is accepted by a switch circuit in the latter half of the writing action respectively. A partial parity is produced from a parity generation circuit 3' in the parity unit to the output of the circuit 2. At the same time, the inspection bit l'' in an error correction code is generated through an error correction code generation circuit 3'' and from the partial parity to the byte of the data (d). Furthermore the syndrome (h) is generated through a syndrome generation circuit 4' and from the information bit (e) applied from the array 1 plus bits l' and l'' applied from the circuits 3' and 3'' respectively. Then the data (d) and the output of the circuit 3'' are held at a register 11, and the parity of the circuit 3' are shared by the circuits 3'' and 4'. In such way, the circuit constitution is simplified. |
