发明名称 CHECKING METHOD OF MEMORY DEVICE
摘要 PURPOSE:To decide a fault of an address bus line, by writing different information in a certain address, and an address whose contents variation of 1 bit becomes equal to said address, and comparing a read-out data and a write data by said certain address. CONSTITUTION:To an address 0 of 3 bits, etc. of an RAM, and addresses 1, 2 and 4 whose contents variation of 1 bit becomes equal to 0, data 1111, 0000, etc. are written respectively. Subsequently, when reading out the address 0, if the second bit, etc. of the address line are opened, an address 3 is designated substantially, and a read-out data becomes 0000. Accordingly, each bit contents of a register Reg 2 is which a write data 1111 is stored and those of a register Reg 1 in which the read-out data 0000 has been stored are compared by an exclusive OR circuit EX, and if conetents of the register Reg 2 have a fault in one of the address bit buses, information 0000 is stored. When the address is grounded, it is executed in the same way, and an address concurrence caused by a fault of an address bus is also decided.
申请公布号 JPS5769599(A) 申请公布日期 1982.04.28
申请号 JP19800145456 申请日期 1980.10.17
申请人 FUJITSU KK 发明人 NISHIKAWA HARUYUKI
分类号 G06F11/00;G06F11/22;G11C29/02;G11C29/10 主分类号 G06F11/00
代理机构 代理人
主权项
地址