| 摘要 |
<p>PURPOSE:To synthesize and to output the element pulses of an optional waveform at an optional time interval by setting a start address of the waveform data and the start address of the data at the generating interval of each element pulse forming a pulse signal. CONSTITUTION:A CPU sets the start addresses at a generating interval data start address register 5 and a waveform data start address register 7 respectively. The generating interval data on a RAM 1 corresponding to the address set at the register 5 is held by a timer register 43. When a counting job is through with a reloading timer 4, the addresses are successively produced from a generating interval data address counter 6. Then the generating interval data on the RAM 1 is sent again to the register 43 and held there. While a waveform address counter 8 produces successively addresses at and after the address set at the register 7 every time the timer 4 finishes its counting action. Thus the corresponding waveform data on the RAM 1 is given to a pulse signal generating circuit 11 and the element pulse signals can be synthesized and outputted.</p> |
