发明名称 DIVIDING CIRCUIT OF PROCESSOR CONTROL SIGNAL
摘要 <p>PURPOSE:To secure the same address for both the memory and device within each peripheral circuit and to facilitate the easy designing of the peripheral circuit, by selecting the control signal of a processor through a combination of the data and the control signal and then connecting the selected control signal to the peripheral circuit with switching. CONSTITUTION:A microprocessor unit 1 is connected to plural peripheral control circuits 7-0-7-n via an address buffer circuit 2 and a data bus two-way buffer circuit 3. Furthermore the reset signal is connected to the clock signal via reset and clock signal driver circuits 5 and 6 respectively. At the same time, a control signal A supplied from the unit 1 is supplied to the circuits 7-0-7-n via a distributing/converging circuit 4, and the control signals are supplied to the unit 1 via the circuit 4. Then the channel selection signal is delivered through the circuit 4 by the signal of a data bus DB when the signal A delivered from the unit 1 is in the prescribed state, and the unit 1 is connected by the signal B given from the circuits 7-0-7-1.</p>
申请公布号 JPS5769329(A) 申请公布日期 1982.04.28
申请号 JP19800143344 申请日期 1980.10.14
申请人 NIPPON DENKI KK 发明人 MURATA HIROSHI
分类号 G06F13/14;G06F13/10;G06F13/42;G06F15/78 主分类号 G06F13/14
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