| 摘要 |
PURPOSE:To obtain an arbitrary delaying quantity without enlarging a circuit scale even when the delaying quantity comes to be larger by cascading plural delaying elements through an alternative selecting gate and controlling the gate. CONSTITUTION:Delaying elements 5-7 are elements to give the delaying quantity of respective 2<n-1>-2<0>.D when a unit delaying quantity is D. To a terminal A of alternative selecting gates 1-4, the digital signal not to be delayed is inputted and to a terminal B, the signal delayed by respective delaying elements is inputted. To a terminal S of respective selecting gates, out of (n) bit data, a first bit is inputted to the gate 1, a second bit is inputted to the gate 2 and hereinafter in the same way, the (n) bit data are inputted. Respective selecting gates make alternative either (the input or output of respective delaying elements) of the signals of terminals A and B by a logic '1' or '0' of respective bits of the (n) bit data. By controlling such a selecting gate as the above- mentioned, the desired delaying quantity can be obtained. |
