发明名称 Power source device for bubble memory unit
摘要 A power source device for a bubble memory unit, wherein there is supplied a first DC voltage Ec which is applied to control circuitry for controlling the reading and writing of data, a second DC voltage signal Ed which is applied to drive circuitry for driving a bubble memory element, and a memory signal Me which enables data to be written in or read from the bubble memory element, the signals Ec, Ed and Me being made to rise and fall according to a prescribed sequence as a commercial power supply is connected and disconnected. The power source device includes first and second DC power source circuits, a comparator circuit for comparing the magnitude of the first DC voltage Ec with a reference level VM having a value greater than an allowable lower limit value, and a delay circuit. The second DC power source circuit is actuated following a prescribed time delay which begins when the value of signal Ec surpasses the reference level VM at the time that the commercial power supply is connected, and the memory enable signal Me is produced after the second DC power source circuit has been actuated. The memory enable signal Me is made to vanish when the magnitude of signal Ec drops below the reference potential Vm at the time that the commercial power supply is disconnected, the second DC power source circuit being rendered non-operational following a prescribed time delay.
申请公布号 US4327422(A) 申请公布日期 1982.04.27
申请号 US19800169791 申请日期 1980.07.17
申请人 FUJITSU FANUC LIMITED 发明人 IMAZEKI, RYOJI;HATTORI, MASAYUKI
分类号 G11C11/14;G06F1/26;G11C19/08;H02H3/247;(IPC1-7):G11C19/08;H04B17/00 主分类号 G11C11/14
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