| 摘要 |
PURPOSE:To achieve high density recording and to simplify the conversion circuit and PLL circuit, by taking the input bit signal in series transmission of binary logical signal into 4-bit information through taking 2-bit 4 type groups. CONSTITUTION:An input bit signal is inputted to a shift register 1 temporarily storing 4-bit, the content of upper rank 2-bit of the register 1 is inputted to a code conversion circuit 2 in parallel and code-converted into 4-bit information. This 4-bit outputs A1-A4 are applied to a 4-bit register 3, the 1st rank bit A1 is applied to the register 3 via exclusive logical sum gates G1, G4, the 2nd upper rank bit A2 is directly, the 3rd rank bit A3 is via the gate G2, and the 4-th rank bit A4 is via gates G3, G5 respectively. The shift clock of the register 3 is taken as twice the period to the shift clock of the input register 1, allowing to serially introduce the 2-bit input data group as 4-bit information and apply the recording magnetic head 22 via an NRZ1 modulation circuit 4. |
