| 摘要 |
<p>A cache oriented pipeline data processing unit includes an execution unit, apparatus for fetching data and instructions, hardware decoder and sequencing circuits and a microprogrammed control unit. The microprogrammed control unit includes first and second control stores. The first control store includes a plurality of storage locations, each location for storing at least an address field and a control sequence field for each of the program instructions required to be executed by the data processing unit. The control sequence field is coded to designate which one of a group of hardware control sequences is to be executed by the hardware sequencing circuits for matching the performance of the execution unit and fetching apparatus. The second control store includes a plurality of groups of storage locations, each group for storing the microinstructions required for executing at least a portion of a program instruction. The microprogrammed control unit in response to each instruction op-code reads out signals corresponding to a control sequence field which are decoded to condition the hardware sequencing circuits for performing those operations required for execution of the instruction. The starting location in the second control store is referenced at the end of the designated hardware sequence and instruction execution proceeds under microprogram control.</p> |
