| 摘要 |
PURPOSE:To reduce power consumption and an are, which the MOS integrated circuit constituting a NAND circuit occupies on a chip, by varying the width of the input gate in this MOS integrated circuit. CONSTITUTION:A load capacity CO is provided in the output part of a two-input NAND circuit, and voltages V1 and V2 are applied to driving transistors TRs 1 and 2, and an output voltage V3 is applied to the gate of a TR0 for load. When the gate of the TR0 is 3mum long and 5mum wide and TRs 1 and 2 are 3mum long together and are 30mum wide and 60mum wide repsectively, the response characteristic of the voltage V3 has rapid rise and fall it the voltage V2 is changed from the H level to the L level at time t=0 or is changed from the L level to the H level at time t=20nsec while keeping the voltage V1 in the H level. |
