发明名称 DIAL PULSE SIGNAL CONVERTER
摘要 PURPOSE:To prolong the feeding time of a dial pulse only by the clock speed ratio by sampling an input dial pulse signal, writing the sampling value in a memory with a fast clock and reading out it from the memory with a slow clock. CONSTITUTION:Input dial pulse sampling values sampled by a sampling clock CLS are written in the location ''0'' of a memory 13 repeatedly until a counter 9 specifies the location ''1'' by a writing clock CLW. In a reading mode, the contents of the location ''0'' are read out repeatedly until a counter 10 specifies the location ''1'' by a reading clock CLR and the contents are transmitted to an output terminal. The time lag between the input and output dial pulses is one read mode for the initial bit. The relation of speed in each clock is CLS>>CLW>CLR.
申请公布号 JPS5767394(A) 申请公布日期 1982.04.23
申请号 JP19800142490 申请日期 1980.10.14
申请人 KOKUSAI DENSHIN DENWA KK 发明人 SHIBA SHIYUUICHI
分类号 H04Q1/32;(IPC1-7):04Q1/32 主分类号 H04Q1/32
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