Magnetic bubble memory control system - uses clock-controlled micro-processor to control operational cycle of bubble memory

摘要

The system utilises a microcomputer controlled by a clock generator (CL). The output of the microcomputer is fed to a latch register (L) that provides the five inputs for control of the bubble memory (BM). A fine control stage (PC) determines the period of control of the bubble memory inputs and interlocks the operation of the microcomputer over a timer (TI) input stage.