| 摘要 |
PURPOSE:To contrive to miniaturize a complementary MOS device by a method wherein at the CMOS device, a connecting hole to connect a P-well to the lowest potential and an electrode are omitted. CONSTITUTION:In the CMOS device, an N type resistance layer 12 is formed at the same time with a source and drain of a N channel MOSFET in the P-well 11 of an N type Si substrate 1, electrodes 3, 4 are fixed to both the edge of the layer 12, and the substrate 1 is held at the highest potential by the electrodes. The resistance value of the layer 12 is set up by sizes L, W. However at this time, the P-well 11 and the N type layer 12 are connected in common with the electrodes 3, 4. By this constitution, when one or plural independent low resistance resistors are to be formed, the hole for electrode and the electrode to connect the P-well 11 to the lowest potential can be omitted. Accordingly the resistance region can be reduced more than the conventional device, andthe device is miniaturized. |
