| 摘要 |
PURPOSE:To obtain a synchronizing signal by frequency-dividing a clock signal which is an integral multiple of a horizontal synchronizing signal, through the detection of ends of a signal outputted from the synchronizing separation circuit such as PCM processor from a clear pulse by muting. CONSTITUTION:A signal outputted from a synchronizing separation circuit 11 is introduced to a differentiation circuit of an edge detection circuit 12, and the output (b) is inputted to a monostable multivibrator M via an NOR gate G, then a horizontal synchronizing signal to noise is muted, and when the output (d) is inputted to the differentiation circuit, a clear pulse is obtained. On the other hand, a clock signal outputted from a signal generating circuit 13 forming the clock signal which is an integral multiple of a horizontal synchronizing signal f0 is frequency-divided while being cleared with a clear pulse at a frequency divider 14 and 42 frequency- division and sequentially at frequency dividers 15, 16. Thus, noise is rejected, dropped-out synchronizing signal is replenished, and a synchronizing signal which is almost in synchronizing with the playback synchronizing signal without delay time can be obtained. |
