| 摘要 |
<p>PURPOSE:To prevent the transfer of erroneous data by performing latching operation only when data on a bus used as both an address bus and a data bus is signified. CONSTITUTION:A latch circuit DLT connected to the bus ADB of a microprocessor muCPU latches data on the bus ADB in the rise of a signal CS. A system clock phi is applied to the clock terminal CK of an FF and an AND circuit AND, and a ''1'' having +5V, etc., normally is applied to the data terminal D; and a signal ALE during address transmission is applied to clear terminal CLR, and an output from a terminal Q is applied to the AND circuit AND and then applied to the latch circuit DLT via an inverter INV. Consequently, the data is signified securely at the rise of a chip selection signal CS, so the data is latched and transferred without any error.</p> |
