发明名称 |
VERFAHREN ZUM HERSTELLEN INTEGRIERTER SCHALTUNGEN |
摘要 |
<p>In a charged-particle-beam lithographic system, charge accumulation on the workpiece during alignment or writing can cause significant pattern placement errors. A film (16) formed directly under the resist layer (56) to be patterned is utilized as a charge-conducting medium during lithography. The pattern delineated in the resist layer (56) is transferred into the film (16) and subsequently into an underlying layer (20). The film (16) is highly compatible with standard lithographic and etching processes used to fabricate LSI and VLSI circuits.</p> |
申请公布号 |
DE3132080(A1) |
申请公布日期 |
1982.04.15 |
申请号 |
DE19813132080 |
申请日期 |
1981.08.13 |
申请人 |
WESTERN ELECTRIC CO.,INC. |
发明人 |
CURTIS ADAMS,ATHUR;BERNARD ALEXANDER JUN.,FRANK;JOSEPH LEVINSTEIN,HYMAN;ROBERT THIBAULT,LOUIS |
分类号 |
H01L21/027;(IPC1-7):01L21/72;01L21/308;05H1/46;03F7/26 |
主分类号 |
H01L21/027 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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