发明名称 ERROR DETECTION SYSTEM
摘要 PURPOSE:To detect the error of an output code where all constituent bits are changed to ''1'' or ''0'', by constituting a code obtained by adding an inversion discrimination bit to binary data with a parity bit added furthermore. CONSTITUTION:Binary data consisting of four data bits D0-D3 inputted to a storage device 11 is supplied from a register 2. This binary data is inputted to not only a parity generating circuit 13 but also a gate 5. The parity generating circuit 13 generaes a parity bit P2 on a basis of odd parity check. Meanwhile, the gate 5 sets an inversion discrimination bit CH to logical 1 when detecting that all data bits D0-D3 are logical ''1'' and sets the inversion discrimination bit CH to logical 0 when detecting that all data bits D0-D3 are logical ''0''.
申请公布号 JPS5762646(A) 申请公布日期 1982.04.15
申请号 JP19800138063 申请日期 1980.10.02
申请人 FUJITSU KK 发明人 TEJIMA TOORU
分类号 G06F11/10;H03M13/00;H04L1/00 主分类号 G06F11/10
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