| 摘要 |
PURPOSE:To make a frequency division circuit unnecessary, by obtaining the alternating pulse having period of two times of set value of a counter circuit by utilizing the flip-flop of the retaining on the higher rank of a counter circuit. CONSTITUTION:In case of periodical hexamerous system counter, flip-flop of the 4th stage of the higher rank of the 4 bits binary counter 1 is retained. Logical output of ''AND NOT'' circuit 2 becomes 0 when the counter value of this circuit is 5, and by the next clock, this hexamerous counter is set in initial condition. Output condition of an output terminal Q3 is read from an input terminal P3 with the inversed condition by the ''NOT'' circuit 3 by performing this clock. Output of the terminal Q3 is inversed. Hereinafter these operations are repeatedly executed. Then, alternating pulse having the period of 12 clocks is obtained at the output terminal Q3, i.e. alternating pulse having the period of two times of the set value in the counter circuit can be obtained. |
