发明名称 PLL CIRCUIT
摘要 PURPOSE:To prevent the fluctuation of oscillation signal of a voltage control type oscillator by switching the frequency division ratio in rising direction of the reference comparison frequency when the frequency division ratio of PLL system is a specified value. CONSTITUTION:Signals sent from a local oscillator circuit 4 are supplied to the phase comparison circuit 13 by passing through a program divider 12. A circuit 13 compares the signals of frequency divided the oscillation frequency of a reference oscillation circuit 14 by using a frequency divider 15A with the output signal of the divider 12, and supplies this result to the circuit 4 and an antenna circuit 1 by passing through an LPF16. While, the end of information of frequency division ratio of the divider 12 stored in the registor 10 is detected by using the lowest digit detection circuit 22. When the lowest digit of the information of frequency division ratio is a special value, switch the ratio of frequency division in rising direction of reference comparison frequency by switching switches 24 and 25 is switched. Therefore, the oscillation frequency is stabilized by decreasing AC included in the output signal of the LPF16.
申请公布号 JPS5761342(A) 申请公布日期 1982.04.13
申请号 JP19800136852 申请日期 1980.09.30
申请人 SONY KK 发明人 UMEDA KAORU
分类号 H03L7/18;H03L7/199;H04B1/26 主分类号 H03L7/18
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