发明名称 MEMORY CONTROLLER
摘要 PURPOSE:To prevent the delay of memory cycle and at the same time to realize a long-time initialize from outside, by subjecting a refresh control circuit to a DMA function and also synchronizing the external clear signal. CONSTITUTION:An access is given to a memory 22 according to the MEMSTART sent from a CPU21 based on the DMAREQ sent from a DMA device 23. At the same time, a control part A24 that forms a refresh control circuit is also started. The DMA device 23 according to a refresh clock is subjected to an apparent functional operation via a refresh counter of the part A24, therefore the memory 22 is refreshed by the REFMODE without competing against the MEMSTART. Accordingly, a racing circuit can be eliminated to prevent the delay of the memory cycle. On the other hand, the external CLEAR signal is synchronized with the refresh clock through a control part B25 to clear the CPU21. Thus the refresh is carried out writhout fail.
申请公布号 JPS5760588(A) 申请公布日期 1982.04.12
申请号 JP19800134079 申请日期 1980.09.26
申请人 TOKYO SHIBAURA DENKI KK 发明人 SATOU KAZUYUKI
分类号 G11C11/406 主分类号 G11C11/406
代理机构 代理人
主权项
地址