发明名称 MONITORING SYSTEM OF SEQUENCE CONTROLLER
摘要 PURPOSE:To display logical operation results at the point in time of monitoring with fidelity, by storing the contents of a bit accumulator in a shift register at every time when arithmetic is performed. CONSTITUTION:The output of a process input equipment 4 is processed by an arithmetic circuit 6 and the result is outputted to a process output equipment 8. Every time when the contents of a bit accumulator 7 are processed, the result is stored in a shift register 10. Once a monitoring command is accepted gy interruption, the contents of the shift register 10 at the specified point in time are displayed on a display device 9.
申请公布号 JPS5759207(A) 申请公布日期 1982.04.09
申请号 JP19800134353 申请日期 1980.09.29
申请人 HITACHI SEISAKUSHO KK 发明人 TAKAKURA MITSUO;SATOU TOMOKATSU;YAMAOKA HIROMASA
分类号 G05B23/02;G06F11/30 主分类号 G05B23/02
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