发明名称 DMA CONTROLLER FOR PACKET LENGTH CONVERSION
摘要 <p>PURPOSE:To contrive the improvement of the processing efficiency by deviating a transfer start address to a next unit buffer by a header length when the end of transfer is a data chain and decreasing the data length to be written by the header length. CONSTITUTION:A modification register 10 storing the header length is provided, an end information storage section 11 is referenced by a control means 12 and when the end of transfer to the preceding unit buffer is finished at the data chain, a value stored in the modification register 10 is added to the transfer start address and the transfer data length is subtracted by a value stored in the modification register 10 and written in the next unit buffer. Since the standard length data is transferred to the next to the header region in each unit buffer, the split is finished by writing the header to the header region. Thus, the processing is attained efficiently without needing the retransfer to the other unit buffer especially.</p>
申请公布号 JPS63212242(A) 申请公布日期 1988.09.05
申请号 JP19870046032 申请日期 1987.02.27
申请人 FUJITSU LTD 发明人 IWAZAWA YUICHI
分类号 H04L29/06;H04L13/00 主分类号 H04L29/06
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