| 摘要 |
PURPOSE:To ensure data sampling accurately, by giving a delay almost equal to a data signal, to a clock line signal via a transmission line before the data sampling point in a receiver from a transmitter. CONSTITUTION:A clock line CRI signal in 16-bit consists of 15-bit consisting of ''1'' and ''0'' consecutiveness at every 3-bit and ''0'' remaining 1-bit. In this cae, a sampling pulse forming circuit 4 is reset with the leading of the second times of the CRI signal. Thus, the CRI signal is subjected to the effect of a low frequency section of group delay characteristics, allowing to the delayed or advanced the same as the data signal. Thus, the sampling pulse formed by taking the 2nd leading of the CRI signal as the time reference can be delayed, and the phase difference with a delayed data signal is made smaller, allowing to compensate the lowering in the ratio of eye height. |
