发明名称 DE-EMPHASIS CIRCUIT
摘要 PURPOSE:To operate a de-emphasis circuit in excellent manner, by detecting the DC level of tip a synchronizing signal to be sampled and adjusting the bias level of a variable bias circuit according to this DC level. CONSTITUTION:A variable bias circuit 2 includes a synchronizing signal and stored on a medium through frequency modulation. The output of this circuit is transmitted to a de-emphasis circuit 3. The synchronizing signal in the output signal of the circuit 3 is sampled with the synchronizing signal from a synchronizing generation circuit 5 and the DC component at the tip of this signal is detected at a sample hold circuit 4. A voltage corresponding to the detected DC level is applied to the circuit 2 through the adjustment of a DC amplifying cirucit 6. Thus, the DC level of the tip of the synchronizing signal to be de-emphasized is kept constant to increase dynamic range and lower the operating voltage.
申请公布号 JPS5758480(A) 申请公布日期 1982.04.08
申请号 JP19800132860 申请日期 1980.09.26
申请人 TOKYO SHIBAURA DENKI KK 发明人 ARAFUNE YASUNARI
分类号 H04N5/922;H04N5/923 主分类号 H04N5/922
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