| 摘要 |
PURPOSE:To increase a time to spare in case of an error correction by H shortening, by providing a latch corresponding to 14-bit 2-word portion, on a correcting operation system, latching an intermediate result of the operation, and executing the correction operation by dividing it into 2 horizongtal synchronizing sections H. CONSTITUTION:This circuit consists of the first SQ generating circuit 12 for executing a calculation before a matrix operation, and the second SQ generating circuit 15 for executing a calculation after the matrix operation and is provided with an SQ latch 14 for latching an intermediate result of the operation, between said circuits. A correcting data which has been read from an RAMI/O bus 1 is corrected extending over 2H, and is rewritten to a bus 1. That is to say, when the n-th correcting data is operated by the first SQ generating circuit 12, a matrix operation of the (n-1)-th correcting data is executed by the second SQ generating circuit 15. According to such constitu tion, when the correcting operation is divided into 2H or longer, an operation time occupied in 1H is shortened, and a time to spare in case of an error correction by H sortening is increased. |
