发明名称 AUTOMATIC EQUALIZER
摘要 PURPOSE:To hold a normal lead-in state stably, by adding a control circuit, which detects a false lead-in state to reset tap coefficients, to an automatic equalizer. CONSTITUTION:A delayed signal and a signal which is not delayed are added by an adding circuit 7. The output of the adding circuit 7 is inputted to a discriminating circuit 8 having two threshold levels. A counter 9 is counted up by the output of the discriminating circuit 8. When counted up n-number times, the counter 9 discriminates false lead-in of an automatic equalizing circuit 2 and outputs a signal (f) which resets tap coefficients of the automatic equalizing circuit 2 to control a delay circuit, and every tap coefficient is reset to the initial state, and the counter itself is reset also.
申请公布号 JPS5757022(A) 申请公布日期 1982.04.06
申请号 JP19800131471 申请日期 1980.09.24
申请人 NIPPON DENKI KK 发明人 KANEMASA FUJI
分类号 H03H15/00;H03H21/00;H04B3/04;H04L25/03 主分类号 H03H15/00
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