| 摘要 |
PURPOSE:To realize high-speed decimal arithmetic without increasing the quantity of hardware, by having a binary arithmetic part and a compensating arithmetic part to carry out simultaneous arithmetic in a decimal arithmetic system that performs arithmetic by adding compensating arithmetic to a calculated numerical value. CONSTITUTION:A binary arithmetic part 12 performs arithmetic based on the numerical value set to arithmetic input registers 15 and 16, and the result of this arithmetic is delivered to an arithmetic output register 17. When the result of arithmetic of the part 12 is 10, a signal (k) is produced to set the necessary compensated value at a compensated value setting part 14. The output of the register 17 is transmitted to a multiplexer (MPX)18, and the compensated value given from the part 14 is transmitted to an MPX19. The numerical values given from the MPXs 18 and 19 are calculated at a compensating arithmetic part 13, and this result of arithmetic is delivered to an arithmetic register 22. When delivering the numerical values transmitted from arithmetic input registers 20 and 21, the MPXs 18 and 19 perform arithmetic based on these values. Both the parts 12 and 13 carry out the arithmetic at a time, and as a result, decimal arithmetic can be performed at a high speed. |
