发明名称 DIGITAL CONTROL ATTENUATOR
摘要 PURPOSE:To obtain a degree of attenuation proportional to the exponential function of the value of a digital control signal by constituting a ladder-type resistance circuit which covers the 1st-bit attenuation stage - (n)th-bit attenuation stage and by turning on and off them through switches. CONSTITUTION:Input terminals 4-1-4-4 for a four-bit binary digital control signal have weights 2<0>, 2<1>, 2<2>, and 2<3>. Switches SWP1-SWP4 are switched by buffer amplifiers 5-1-5-4 performing opening and closure drive, and output signals of those buffer amplifiers 5-1-5-4 are inverted by inverters 6-1-6-4 to open and close corresponding switches SWS1-SWS4. Then, when the switches SWS1-SWS4 are off and the SWP1-SWP4 are also off, and when the switches SWS1-SWS4 are off and the SWP1-SWP4 are on, degrees of attenuation at respective attenuation stages are K, K<2>, K<4>, and K<8> (K=RP/(RP+RO) and RP=RP1-RP48).
申请公布号 JPS5755606(A) 申请公布日期 1982.04.02
申请号 JP19800130925 申请日期 1980.09.19
申请人 MATSUSHITA DENKI SANGYO KK 发明人 UYA MASARU
分类号 H03H7/24 主分类号 H03H7/24
代理机构 代理人
主权项
地址