| 摘要 |
In this circuit arrangement of a logic unit, a program memory with a capacity of (2<K>) storage locations with in each case (L + M + 1) bits, a K-bit binary counter and with an input/output unit which is composed of several modules having in each case (2<(L+1)>) inputs and in each case (2<(L+1)>) outputs, the input (CLOCK) of the M-bit binary counter (6) is connected to the output (RESET) of the logic unit (1) and the K-bit binary counter (3), and the outputs (Q1, Q2, ... QM) of the counter (6) are connected to the inputs (V1, V2, ... VM) of the decoder-demultiplexer (8) and the inputs of the input/output unit (5) of the programmable logic control unit, the output of the latter being connected to the input (UP/DOWN) of the counter (6). The input (E) of the decoder-demultiplexer (8) is connected to the output (a) of the first logic circuit (7), the second output (a) of which is connected to the input (E) of the decoder-demultiplexer (9) and the inputs (V1, V2, ... VM) of the first logic circuit (7) and of the decoder-demultiplexer (9) are connected to the outputs (MSB) of the program memory (2) whilst the output (I1) of the decoder-multiplexer (8) is connected to the output [ME(1)] and some of the outputs [I2, I3, ... I(2M-T)] of the decoder-demultiplexer (8) are connected to the inputs (b) of the other logic circuits (10). <IMAGE>
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