发明名称 UN APARATO DE ANTIRREBOTE Y ALMACENAJE DIGITAL PARA UN SIS- TEMA DE CONMUTACION TELEFONICA
摘要 <p>A digital debouncing and storage apparatus operates on the receiving end of a digital carrier span line used in a telephony system to couple a multiplex signal to a receiving site to be used by the switching network control. Incoming signaling bits of the multiplex signal are stored in a random access memory at a particular storage location reserved for each channel contained in a group. There is also stored at the location previous timing information concerning each sampling bit. The circuit operates to time any change in the value of a status bit to insure that it lasts long enough to indicate a valid change of state. An up/down counter serves to time each status bit during predetermined signaling frames based on a count inserted into the counter indicative of the timing information as stored in memory. Thus each channel associated with the multiplex signal has stored in memory a unique status bit as well as timing information pertinent to that bit. The circuit operates over a predetermined number of frames whereby if the status of the bit has changed between one binary value to another, the circuit will recognize such a change only after a given number of signaling frames have elapsed. In this manner, contact bounce or channel interference which may effect the signaling bit is eliminated from interferring with system operation.</p>
申请公布号 ES502779(D0) 申请公布日期 1982.04.01
申请号 ES19790005027 申请日期 1981.06.04
申请人 STANDARD ELECTRICA SA 发明人
分类号 H04J3/10;H04J3/12;H04Q11/04;(IPC1-7):04Q11/00 主分类号 H04J3/10
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