发明名称 HANDOTAIKIOKUSOCHI
摘要 <p>PURPOSE:To realize the relief for a writing defective bit, by storing the address information of a defective bit to which a writing defect is caused at a P-ROM into a redundant P-ROM. CONSTITUTION:When an output signal O1 is set at ''0'' at the moment the writing is carried out to a P-ROM11, a redundant P-ROM12 is made active. Then the address information ''1'', i.e., address signals A0=0 and A1=1 are written. Thus the ROM12 stores the address information of a defective bit plus the information showing that the ROM12 is active. After this, a detecting circuit 13 works by the active information output AC given from the ROM12 when the information of address ''1'' of the ROM11 is read. Then a coincidence detection signal of the output of the circuit 13 is transmitted to a clamping circuit 17 to obtain an output of ''1'' level at an output terminal OUT.</p>
申请公布号 JPS5753899(A) 申请公布日期 1982.03.31
申请号 JP19800128854 申请日期 1980.09.17
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 MYAMOTO JUNICHI
分类号 G11C17/00;G06F9/06;G06F12/16;G11C29/00;G11C29/04 主分类号 G11C17/00
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