发明名称 YOMIDASHISENYOKIOKUSOCHI
摘要 <p>PURPOSE:To relieve the write-in defect without giving any effect to the peripheral circuits, by connecting the collector of an npn transistor to a power source and a chip selection signal line via a diode. CONSTITUTION:The collector region of an npn transistor 11 forming a memrory cell of a PROM is made common, and the emitter of the transistor 11 is connected to a bit selection line BL via a fuse 12, and the base is connected to a word selection line WL respectively. At the same time, the collector region is connected to a power source VCC via a diode 13 as well as to a chip selection terminal CS via a diode 14. When a write-in defect arises, the voltage applied to the fuse 12 increases to blow the fuse 12. In this instant, the backward voltage is applied to the diode 13 to prevent the detouring of current to the source VCC from a terminal CS.</p>
申请公布号 JPS5753893(A) 申请公布日期 1982.03.31
申请号 JP19800128853 申请日期 1980.09.17
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 SAITO SHINJI
分类号 G11C17/00;G11C17/08;G11C17/18 主分类号 G11C17/00
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