| 摘要 |
PURPOSE:To reduce the occupancy area on the subject device by a method wherein the connecting wires between elements are reduced in the CMOS logic circuit which is integrated on a semiconductor chip. CONSTITUTION:A P type Si layer 2 is epitaxially formed on a substrate 1 and an insulating isolating layer 3 reaching the substrate 1 is formed by performing a selective oxidation using a nitriding Si film. Then, an N<+> diffusion layers 4a and 4b are formed in a P type Si layer 2 and the surface of the diffusion layers is covered by a thick oxide film. Subsequently, the oxide film 5 located in the central part is removed, a thin oxide film is provided and a nitriding Si layer 7, which will be used as a master slice, is provided on a part of the thin oxide film. Accordingly, as the CMOS element is constructed in a chip, the connecting wirings between elements are reduced and the CMOS logic circuit device having a reduced occupancy area can be obtained. |
