| 摘要 |
<p>PURPOSE:To obtain a continuous clock synchronous with an intermittent clock in the data in a stable way, by supplying an apparent continuous clock signal into a phase locked loop PLL circuit to perform a consecutive comparison of phase. CONSTITUTION:A D type flip-flop D-FF2 is set with the differential output of a differentiating circuit 9 to decide the point of initiation for the comparable range of phase. Then the D-FF2 is reset when the clock information gets into the comparable range. If no clock information gets into the comparable range, the output of a voltage control oscillator 8 is reset with a delayed signal. Accordingly if the clock information is within the comparator range, this information functions as the input of a phase comparator 6. Otherwise the output of PLL circuit 5, i.e. the output of the oscillator 8 is supplied to the comparator 6. In such constitution, the asynchronous clock getting into the phase comparable range can be reduced. As a result, a continuous clock synchronous with the intermittent clock in the data can be stably demodulated.</p> |
