发明名称 JIFUNWARIDAJUSHINGODENSOSHISUTEMUNOSHIKYOKUNAIBUKAIROSOCHI
摘要 PURPOSE:To completely prevent malfunction due to noise mixed during transmission, by avoiding output to terminals until all of control signals are received to a selected slave station, discriminating if noise comes for the time, and outputting the control signal to the terminal depending on the presence. CONSTITUTION:A signal transmitted from a master station enters a wave shape circuit in a slave station and divided into CP1, CP2, and DATA signal. These signals are transmitted to a serial-parallel conversion circuit 1, and if the address detection circuit coincides at the 1st 8-th bit, a signal AD is outputted. This AD signal is led to a serial-parallel circuit 5 via FF2 to be set and an AND circuit 4, and the circuit 5 is controlled with a signal SRO. If noise is mixed, a signal NG is transmitted to an FF3 from a noise detection circuit, and an output NOL from the FF3 resets an FF8 via an OR circuit 10 to make zero the SPO output of an AND circuit 7. Thus, the gate of a tri-state buffer 9 remains closed and a stored control signal is not outputted to the terminal.
申请公布号 JPS5754449(A) 申请公布日期 1982.03.31
申请号 JP19800130425 申请日期 1980.09.19
申请人 NIPPON FUREKUTO KK 发明人 SASAHARA JUNICHI;TAKENAKA TAKESHI;TAKESHIMA MICHUKI
分类号 H04B1/10;H04L5/22 主分类号 H04B1/10
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